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| S1008V1C WCFS1008V1C 128K x 8 Static RAM Features * High speed -- tAA = 12ns * CMOS for optimum speed/power * Center power/ground pinout * Automatic power-down when deselected * Easy memory expansion with CE and OE options Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS1008V1C is available in standard 400-mil-wide package. Functional Description The WCFS1008V1C is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Logic Block Diagram Pin Configurations SOJ Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 ROW DECODER I/O2 SENSE AMPS 512 x 256 x 8 ARRAY I/O3 I/O4 I/O5 I/O6 CE WE OE COLUMN DECODER POWER DOWN I/O7 Selection Guide WCFS1008V1C 12ns Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 160 5 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 Revised April 19, 2002 WCFS1008V1C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage .................................-0.5V to VCC + 0.5V [1] Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0C to +70C VCC 3.3V 10% Electrical Characteristics Over the Operating Range WCFS1008V1C 12ns Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = - 4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 160 Max. Unit V V V V A A mA ISB1 20 mA ISB2 5 mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. 2 WCFS1008V1C AC Test Loads and Waveforms 3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R1 480 R1 480 3.3V OUTPUT R2 255 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3 ns ALL INPUT PULSES 3.0V 90% 10% 90% 10% 3 ns Equivalent to: THEVENIN EQUIVALENT 167 1.73V OUTPUT Switching Characteristics[4] Over the Operating Range WCFS1008V1C 12ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE[7, 8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[5, 6] 12 9 8 0 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High Z[5, 6] 3 6 0 12 Z[5, 6] CE LOW to Low Z[6] CE LOW to Power-Up CE HIGH to Power-Down 0 6 3 12 6 12 12 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 3 WCFS1008V1C Data Retention Characteristics Over the Operating Range Parameter VDR tCDR tR [3] Description VCC for Data Retention Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 0 200 Max. Unit V ns s Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 4 WCFS1008V1C Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 14 tHZOE Notes: 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. tHD DATAIN VALID 5 WCFS1008V1C Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[13] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 14 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H X L L L OE X X L X H WE X X H L H High Z High Z Data Out Data In High Z I/O0-I/O7 Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code WCFS1008V1C-JC12 Package Name J Package Type 32-Lead 300-Mil Molded SOJ Operating Range Commercial 6 WCFS1008V1C Package Diagram 32-Lead (400-Mil) Molded SOJ J 51-85041-A 7 WCFS1008V1C Document Title: WCFS1008V1C 128K x 8 Static RAM REV. ** Issue Date 4/15/02 Orig. of Change XFL Description of Change New Datasheet 8 |
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